1. Field of the Invention
The invention relates to a task scheduling method, more particularly to a task scheduling method for low power dissipation in a system chip.
2. Description of the Related Art
At present, mobile devices, such as mobile phones, personal digital assistants (PDAs), etc., are in wide use. However, while these devices require numerous transistors in a System-on-a-Chip (SOC) so as to achieve the purposes of lightweight and compact dimensions, the large number of transistors or logic gates results in escalation in power dissipation. If the problem of power dissipation is not resolved, prolonged use of the mobile devices can result in instability due to overheating of the same.
Power dissipation in electronic components may be attributed mainly to static power dissipation caused by leakage current loss in a complementary metal-oxide-semiconductor (CMOS) circuit, or dynamic power dissipation caused by switching transient currents and charging/discharging of capacitive loads.
The following equation is used for static power dissipation (Pstatic) estimation:Pstatic=Vdd×N×kdesign×Ileakage   Equation (1)
wherein Vdd is an input transistor voltage, N is the number of transistors, kdesign is a design-dependent constant, and Ileakage is the leakage current caused by reverse bias leakage of the integrated circuit.
The following equations are used for dynamic power dissipation (Pdynamic) estimation:Pdynamic=C×α×f×(Vdd)2   Equation (2)f=k×(Vdd−Vt)2/Vdd   Equation (3)
wherein f is the operating clock frequency, C is the load capacitance, α is the switching activity, k is a circuit-dependent constant, Vdd is an input transistor voltage, and vt is the threshold voltage.
Due to the aforesaid factors of static and dynamic power dissipation existing in transistors of a system chip, it is very critical to lower downpower consumption of the system chip. Through the design of low-power circuits and dynamic power management, a system chip can be prevented from reaching high temperatures or even overheating under normal operating conditions so as to reduce the problem of heat dissipation. Hence, manufacturers need not incur additional expense during chip packaging for overcoming the heat-dissipation problem of system chips while enhancing circuit reliability and prolonging the service lives of the system chips.
To reduce power consumption of a system chip, many research papers and patents in the field of variable voltage scheduling techniques are available. For instance, “Task scheduling for low-energy systems using variable supply voltage processor” made public in the Asia and South Pacific Design Automation Conference (ASPDAC) in 2001, and “Variable voltage task scheduling for minimizing energy or minimizing power” made public in the International Conference on Acoustics Speech, Signal Processing (ICASSP) in 2000 both proposed task scheduling methods and devices for low power dissipation through dynamic voltage scaling for lowering down the overall energy consumption of a system chip.
U.S. Pat. No. 5,831,864, titled “Design tools for high-level synthesis of a low-power data path”, and U.S. patent Publication No. 2003/0217090, titled “Energy-aware scheduling of Application execution”, disclose data paths and principles for scheduling tasks associated with the lowest power dissipation on multiple processing elements (PEs). In U.S. patent Publication No. 2003/0217090, there is disclosed a mobile device that manages tasks using a scheduler for scheduling tasks on multiple processors. The scheduling method involves initial scheduling of tasks based primarily on energy consumption criteria, then dispatching the tasks to different processors according to the deadlines thereof so as to obtain an optimum scheduling result with lowest power dissipation.
Nevertheless, the prior art only disclose methods for scheduling tasks on different PEs of a system chip to minimize power consumption of the PEs. The applicants are unaware of any prior art that also takes into consideration non-PEs, such as I/O interfaces, control circuits, etc., of a system chip during task scheduling. It is well known in the art that, during execution of tasks, the task processing efficiency is dependent upon the relationships between PER and non-PEs. Therefore, if task scheduling only took PEs of the system chip into consideration and excluded all non-PEs, the estimated result of overall power dissipation of the system chip is most likely to be imprecise.